https://wiki2.ztex.de/ Wed, 08 Apr 2026 00:36:31 +0000 FeedCreator 1.8 https://wiki2.ztex.de/lib/tpl/sidebar/images/favicon.ico https://wiki2.ztex.de/ https://wiki2.ztex.de/doku.php?id=en:ztex_boards:ztex_fpga_boards:memfifo:memfifo&rev=1480030461&do=diff memfifo Example for Series 2 FPGA Boards It is a more complex example for Series 2 FPGA Boards which demonstrates * High speed EZ-USB -> FPGA transfers using the Slave FIFO interface * High speed FPGA -> EZ-USB transfers using the Slave FIFO interface * Usage of external SDRAM (if available on FPGA Board) or internal BRAM anonymous@undisclosed.example.com (Anonymous) en:ztex_boards:ztex_fpga_boards:memfifo Thu, 24 Nov 2016 23:34:21 +0000 https://wiki2.ztex.de/doku.php?id=en:ztex_boards:ztex_fpga_boards:memfifo:usb_fpga_2_04&rev=1406580871&do=diff Memory tutorial for USB-FPGA-Modules 2.04 This tutorial explains the generation of the memory controller IP Core for for the memfifo Example USB-FPGA-Modules 2.04. Creating the IP Core This section describes how the IP Core is created using MIG version 13.41 (ISE Version 14.7). The settings for other versions should be very similar. anonymous@undisclosed.example.com (Anonymous) en:ztex_boards:ztex_fpga_boards:memfifo Mon, 28 Jul 2014 20:54:31 +0000 https://wiki2.ztex.de/doku.php?id=en:ztex_boards:ztex_fpga_boards:memfifo:usb_fpga_2_13&rev=1698700836&do=diff Memory tutorial for USB-FPGA-Modules 2.12, 2.13, 2.14 and 2.18 This tutorial explains the generation of the memory controller IP Core for for the memfifo Example USB-FPGA-Modules 2.12, USB-FPGA-Modules 2.13, USB-FPGA-Modules 2.14 and USB-FPGA-Modules 2.18. Creating the IP Core This section describes how the IP Core is created using MIG version 2.1 (Viavado Version 14.2). The settings for other versions should be very similar. anonymous@undisclosed.example.com (Anonymous) en:ztex_boards:ztex_fpga_boards:memfifo Mon, 30 Oct 2023 21:20:36 +0000